1. Field of the Invention
The present invention generally relates to central processing units (CPUs) such as a microprocessor for performing a pipeline process and, more particularly, to a central processing unit for performing a pipeline process at an increased processing speed.
2. Description of the Related Art
A pipeline process is used as one of the means to improve the performance of a central processing unit such as a microprocessor. A pipeline process is designed to reduce a time required for processing each instruction when a plurality of instructions are successively executed, by dividing a sequence that includes reading, encoding and executing an instruction into different stages, and by concurrently performing stages of the plurality of instructions.
When a CPU executes an instruction, the CPU must specify data to be used in the execution, that is, the CPU must specify an address of an operand. The CPUs are characterized by different modes of addressing (methods of specifying addresses). An address of an operand for a given instruction is specified using one of the addressing modes provided by the CPU executing the instruction. In executing an instruction, the CPU calculates the address (effective address) of the operand for the instruction in accordance with the addressing mode for the instruction and using address data specified by the instruction.
An arithmetic unit is used as required in order to calculate the effective address. A CPU not provided with an arithmetic unit dedicated to address calculation uses an arithmetic and logic unit (ALU) used for computation using an operand (data process) in order to calculate an address. In such a case, computation using the operand and address calculation are processed in the same stage in the pipeline. As a result, address calculation of an instruction has to wait until computation using an operand for a preceding instruction is completed. A further description will be given with reference to a timing chart of FIG. 1.
FIG. 1 is a timing chart showing a pipeline process performed by a central processing unit according to the related art which is not equipped with an arithmetic unit dedicated to address calculation.
The process of FIG. 1 comprises an instruction fetching stage, a decoding stage and a computational stage. In cycle 1, an instruction A is decoded and a next instruction B is fetched. In the next cycle 2, data processing for the instruction A is performed and the instruction B is decoded. Since the central processing unit is not equipped with an arithmetic calculation unit dedicated to address calculation, it cannot calculate an address of an operand for the instruction B in cycle 2. Therefore, the address calculation for the instruction B is performed by the ALU in the next cycle 3. The computation for the instruction B is performed in the next cycle 4. If any of the stages is executed twice or more for an instruction as shown in FIG. 1, where the computational stage performed by the ALU is executed twice for the instruction B, the stages (in this case, the instruction fetching stage and the decoding stage) preceding the stage executed a multiple of times has to wait, thereby stalling the operation.
One approach to avoiding such a halt may be to assign address calculation and computation using the operand to different stages. With this arrangement, when an instruction is in the computational stage, an address of an operand for a next instruction can be calculated at the separate address calculation stage.
However, such an approach requires an arithmetic unit dedicated to address calculation (hereinafter, referred to as an address arithmetic unit) to be added to the CPU since the ALU cannot be used for address calculation. An address arithmetic unit should be capable of performing an address calculation for all types of addressing modes provided by the CPU. In case a complex addressing mode is provided, the construction of the address arithmetic unit and associated data routes become accordingly complex. For example, when a target address is produced by adding a register value to another register value, data routes from these registers to the address arithmetic unit should be provided. If one of the values to be added to produce a target address is an immediate value set in the instruction code instead of a register value, a data route for feeding the immediate value to the address arithmetic unit should be provided. If a plurality of calculations are necessary in order to obtain a target address, means for temporarily storing a calculation result and a data route for supplying the calculation result back to the address arithmetic unit should also be provided.
If an address of an operand is calculated according to an addressing mode using a specific register provided in the CPU as a base register, a problem associated with a write-after-read hazard must be considered. The write-after-read hazard occurs when an instruction updates a value in a register provided in the CPU. A subsequent instruction should use an updated value. When a plurality of stages of a pipeline process overlap, however, there is a likelihood that the subsequent instruction refers to the register before the preceding instruction has time to update the value. This problem may be overcome by detecting a write-after-read hazard and stalling the subsequent stages, or by forwarding the data to be updated to the subsequent stage bypassing the register.
As described above, assigning address calculation and computation using an operand to different stages requires an address arithmetic unit adapted for all types of addressing provided by the CPU, resulting in an increase in the circuit scale or requires more complex pipeline process control in order to deal with the problem associated with a write-after-read hazard in the pipeline process. As a result, the CPU cost is increased.